(1) Field of the Invention
The present invention relates generally to electrically erasable nonvolatile semiconductor memories and semiconductor devices having structures useful for the fabrication of circuits used for the same, and more particularly to a nonvolatile semiconductor memory of the configuration that eases the dielectric strength requirements, and a semiconductor device having such a circuit configuration, and further, to a semiconductor device that serves to simplify the fabrication process.
(2) Description of the Related Art
Electrically rewritable nonvolatile memories include, for example, E.sup.2 PROM; and among others, flash memory having total or selective total erasure capabilities has been attracting attention in recent years because of its high bit-density capabilities.
The memory cell of the flash memory has a two-layered gate structure consisting of a control gate and a floating gate, in which information storage is accomplished by utilizing the property that when prescribed voltages are applied to the control gate, drain, and source, the current flowing between the drain and the source varies depending on whether or not a charge is stored on the floating gate. Generally, in flash memories, injecting a charge into the floating gate is called writing.
For writing, a high voltage VPP (about 12 V) is applied to the control gate, about 6 V is applied to the drain, and 0 V is applied to the source. Under these conditions, electrons flowing through the memory cell encounter a high electric field near the drain, and part of the electrons, accelerated by this field, gain enough energy to overcome the energy barrier of the gate insulating film and are injected into the floating gate. Since the floating gate is electrically isolated from other circuit regions, the injected charge can be stored thereon semipermanently.
For reading, a supply voltage VCC (about 5 V) is applied to the control gate, about 1 V is applied to the drain, and 0 V is applied to the source. The threshold voltage of the cell transistor varies depending on the presence or absence of a charge on the floating gate, so that the current flowing through the selected memory cell varies accordingly. By sensing and amplifying this current, the information is read out.
There are two main methods of erasure: one is the channel erasure method in which the charge stored on the floating gate is drawn into the channel, i.e., into the substrate or a well, and the other is the source erasure method in which the charge is drawn into the source.
In channel erasure, 0 V is applied to the control gate, the drain and source S are left open, and a high voltage VPP (about 12 V) is applied to the channel (p-well). This causes the charge stored on the floating gate to be drawn into the channel. In source erasure, the high voltage VPP is applied to the source, and the channel is left opened or connected to ground.
The recent trend for semiconductor devices has been toward lower supply voltages, and the reduction of supply voltages has also been pushed forward for flash memories. The lower voltage design also requires the reduction of the high voltage applied to the channel or source for erasure. In a single-voltage device, a booster circuit is used to produce the high voltage, but the problem here is that when the supply voltage is reduced, the booster circuit must be made larger accordingly.
In the source erasure method, since a high potential is applied to the source, the source diffusion layer must be formed a greater depth to provide enough dielectric strength to sustain the high potential. This has impeded the effort to reduce the cell area.
Furthermore, for selective erasure, the circuit must be designed so that the source connection line (VSS line) can be set partially at a different potential. This requires line isolation and the addition of an extra drive circuit, and the chip size is increased accordingly.
To overcome these problems, there has been proposed a negative voltage application erasure method in which a negative voltage is applied to the control gate to allow a reduction in the positive voltage applied to the channel or source. This method is becoming a predominant method for erasure.
Usually, the negative voltage VBB to be applied to the control gate is set to about -10 V, and the supply voltage VCC of 5 V is applied to the channel or source.
The basic operation of the flash memory has been described above. Nonvolatile memories, such as flash memory, require a high-voltage power supply in addition to the conventional power supply; therefore, for circuits operating at high voltages, high-voltage transistors need to be fabricated in addition to normal-voltage transistors.
Depletion-mode transistors as well as enhancement-mode transistors are widely used in power supply circuits and the like. The above two types of transistor are distinguished from one another based on the presence or absence of the channel with zero gate bias. In an enhancement-mode device, no channel exists with zero gate bias; in a depletion-mode device, the channel exists with zero gate bias.
In the case of the depletion-mode transistor, however, since the channel is formed when no gate bias is applied, as described above, the control by the gate bias is complex compared with the enhancement-mode transistor. Therefore, circuit design is usually done based on enhancement-mode devices.
This does not, however, preclude the use of depletion-mode transistors from the circuit design; depending on applications, far more efficient circuit design may be done using depletion-mode devices rather than using enhancement-mode ones. Constant-voltage sources and signal switching devices (transfer gates) are specific examples.
Erasure of a flash memory is accomplished by drawing electrons from the floating gate into the channel or into the source by making use of the quantum tunnel effect. However, the current (tunneling current) caused by the electrons being drawn varies exponentially with the field strength between the floating gate and the channel or the source. As previously noted, for semiconductor devices including flash memories, the trend is toward lower supply voltages, and furthermore, increasing numbers of semiconductor devices are being designed for use with a single power supply. In the flash memory erasure methods using the negative voltage application method, the supply voltage VCC is directly applied to the channel or to the source. In the case of a semiconductor device designed for use with a 3-volt single power supply, for example, if this supply voltage were directly applied to the channel or to the source, the resulting field strength would be smaller than that with a 5-volt power supply. As described above, the field strength between the floating gate and the channel or the source greatly affects the tunneling current. To obtain the same erasure efficiency as in 5-volt devices, an electric field of the same strength as when a 5 V supply voltage is applied must be applied to the tunnel oxide film; if the 3 V supply voltage is applied to the channel or the source, a large negative voltage, which is large in terms of the absolute value, will have to be applied to the control gate. This means application of a large voltage to the oxide film of each transistor used in a booster circuit that generates the large negative voltage, which causes a problem in that it puts extra demands on the voltage withstanding characteristic (reliability) of the transistor.
In semiconductor devices, such as flash memories, that require high voltages, normal-voltage and high-voltage circuits are mixed in the same circuitry. Two kinds of transistors, i.e. 5-volt transistors and 12-volt transistors, are formed in a selective manner, the 12-volt devices being formed in only part of the whole integrated circuit. This, however, increases the complexity of processing and makes the fabrication more difficult.
As previously described, effective circuit design can be realized using depletion-mode transistors for such a power supply circuit as described above. To implement a depletion-mode transistor, a wafer process-like technique is usually used. That is, a large number of charges of the same polarity as the charges that form the channel are distributed in the channel region of a MOS transistor. For example, in the case of an n-channel depletion-mode transistor, the device is formed so that its channel region predominantly contains charges of negative polarity; conversely, a p-channel depletion-mode transistor is formed so that charges of positive polarity are predominant in its channel region. In practice, to provide the MOS transistor channel region with the above charge profile, p- or n-type impurities are ionized and accelerated by a field for injection into the channel region. This technique is generally called ion implantation.
Ion implantation is not only used for the formation of depletion-mode transistors, but the same technique is also used for forming n-channel and p-channel enhancement-mode transistors usually used as circuit elements. However, since enhancement-mode and depletion-mode devices require different charge distributions in the channel region, the charge distribution in the channel region is adjusted by varying the ion dose, the kind of ion implant, the field strength, etc. This means that the fabrication of deletion-mode transistors inevitably involves increased kinds of ion implants in the wafer processing steps. An increased number of processing steps causes such problems as increased complexity of the wafer process and increased time for process setup, leading finally to increased costs of the semiconductor devices.